Stochastic-based logic circuit synthesis and implementation through large-fanin threshold logic with magnetic tunneling junctions

The logic design framework based on Threshold Logic Gate (TLG), combined with emerging spintronic device technology, can achieve ultra-high-performance computing circuits. However, large-fanin threshold logic gates with emerging devices often lead to reduced variation tolerance for memristance, therefore resulting in a so-called fan-in restriction problem. This limitation prevents both large threshold logic nodes and further reduction of logic depth, both of which are critical to achieving high circuit performance. In this paper, we propose a novel stochastic-based design methodology for large-fanin threshold logic gates and two specially designed CAD algorithms to calculate probabilistic weights and threshold values. These techniques allow us to design and implement efficient and robust logic circuits with very large fanin and very shallow logic depths. Our simulation results have shown that, for seven ISCAS-85 benchmark circuits, on average, the energy consumption and delay performance can be improved by about 50% and 30% when comparing our stochastic-based design with a deterministic memristor-based threshold logic design. In addition, for the same set of benchmark circuits, our stochastic-based spintronic circuits can be more than 100x more energy efficient than the conventional CMOS-based FPGA.