Verification and management of a multimillion-gate embedded core design

Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design using HW-simulation and cycle simulation-based HW/SW-coverification. The main focuses are overall methodology, testbench management, the verification task itself and defect management. The chosen verification process was a real success: the quality of the designed hardware and software was increased and furthermore the time needed for integration and test of the design in the context of the overall system was greatly reduced.