Optimized Memristor-Based Multipliers

Since memristors came to the forefront of research, minimal work has explored their application to computer arithmetic. This paper proposes two memristor-based implementations of an N-bit shift-and-add multiplier, one using IMPLY operations and a second using MAD operations. The optimized IMPLY-based implementation reduces the baseline delay from 2N
²
+ 29N steps and 17N+3 memristors to 2N
²
+ 21N steps and 7N+1 memristors. A second implementation is proposed that is constructed from MAD gates, a lower-area, lower-delay alternative to IMPLY logic. This design performs an N-bit multiplication in N
²
+ N steps with 5N memristors and 3N+2 drivers. Both designs require fewer steps and less than 1/6 of the number of components of a traditional CMOS design. Finally, both of the implementations are extended to implement radix-2 Booth multipliers. The IMPLY design only increases by 1 step per iteration and 2N memristors and drivers. The MAD design increases by N memristors and 6N switches but maintains the same delay as the shift-and-add multiplier. Both designs maintain a lower area and lower delay than the CMOS equivalent.