Design of Vedic IEEE 754 floating point multiplier

Floating point number can co-occurrently develop a prominent range of numbers and a high level of precision. Multiplication of floating point numbers found extensive use in wider range of technological and commercial calculations. It is needed to implement faster multipliers involving limited area and consuming reduced power. An IEEE-754 format established multiplier applying Vedic Urdhva - Tiryagbhyam mathematics will be cultivated to cover both single precision and double precision format floating point numbers in the paper. This paper proposes a floating point multiplier which manages overflow, underflow and rounding. The proposed and conventional floating point multipliers based on Vedic mathematics would be coded in Verilog, Synthesized and Simulated using ISE Simulator. Xilinx Virtex VI FPGA will be used for Hardware realization and Verification. It is proposed to compare resource utilization and timing performance of the proposed multiplier with that of existing as of now.