Modular approach for customizable UART

This paper proposes a technique for implementing a UART (Universal Asynchronous receiver transmitter) with a new architecture such that the whole core can be modified for our desired specifications and can be integrated in a bigger design, wherever UART is necessary. This paper is implementing the design through Verilog HDL using Xilinx 14.2 design suite and it is tested on Spartan-6 FPGA after interfacing the circuit under test using PC with the help of RS-232 cable. The simulation results and the test results are supporting our proposal.