Design of 1-bit and 4-bit adder using reversible logic in quantum-dot cellular automata

Limitations of present complementary metal oxide semiconductor (CMOS) technology are heat dissipation, power dissipation, scaling problem and performance degradation. These problems can be resolved by adopting new emerging technologies like quantum-dot cellular automata (QCA) and reversible logic technology, which provides a new horizon in low power computation. Reversible logic technology handles heat dissipation problem very effectively whereas remaining problems can be easily taken care by QCA. Here, full adder and 4-bit ripple carry adder (RCA) are implemented using Peres gate (PG). QCADesigner tool has been used for designing of Peres gate, full adder and 4-bit RCA. The proposed Peres gate requires 137 cells which covers an area of 0.13μm² with one clock cycle delay. The proposed full adder is evaluated and achieves 60%, 19.7% and 50% improvement in area, complexity (no. of cells) and delay respectively. Similarly proposed 4-bit RCA gains significant improvement in terms of area, complexity and delay.