High-speed interfaces for analog, iterative VLSI decoders

The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature as well as their power and area efficiency. It is expected that data rates well above 100 MS/s can be obtained.