Capacitor mismatch error cancellation technique for a successive approximation A/D converter

An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, the first order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated op amp is explained. SWIT-CAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under nonideal conditions, including 1% 3/spl sigma/ nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB op amp gain, and 30 mV op amp offset.