Systematic Investigation of Self-Heating Effect on CMOS Logic Transistors From 20 to 5 nm Technology Nodes by Experimental Thermoelectric Measurements and Finite Element Modeling

The characteristics of thermal conductivity(k) with different operated temperatures (T), material thicknesses (t), and impurity concentrations (N) are studied by thermoelectric measurements and developed simulation model for the study of self-heating effect. With the input of these module-level material properties in our developed finite-element model, the self-heating effect on the CMOS logic transistors from 20to 5-nm technology nodes are investigated systematically and accurately. The maximum chip temperature in the 14/16-nm technology node Si FinFET device is ~170 °C. On the other hand, the higher operated temperature is also observed in high mobility material devices such as Ge and III-V (InAs) FinFETs due to their poor material properties of k-value. It indicates that these high mobility materials are hard to be used in the next generation scaled technology node devices, unless these devices can be operated at the ultralow voltage bias (<;0.5 V for InAs and <;0.8 V for Ge) from the self-heating effect point of view.