A 6 GHz, 1.8 V, divide-by-2 circuit implemented in silicon bipolar technology

This paper presents a divide-by-2 circuit in current mirror control logic (CMCL) topology, operating up to 6 GHz at low voltage supply. The total measured power consumption is approximately 7 mW (excluding the 50 /spl Omega/ output driver) at 1.8 V with 2.7 mW/latch including the current mirrors. The CMCL topology allows a clock switch using only two cascaded transistors and is therefore suitable for low voltage applications of portable systems. The circuit has been designed for nominal 2 V operation and has been implemented in a high performance production bipolar technology.