A survey on replacement strategies in cache memory for embedded systems

Cache is one of the most power-consuming components in computer architecture. Power reduction in cache can be achieved by reducing miss rate miss penalty latency per access and power consumption per access. The power reduction can also be achieved by shutting down unused part of the cache by allowing not so recently used cache banks to sleep reconfiguring the cache for specific application and various combinations of one or more of these. The cache hit depends on the cache size associativity and the cache line size. Replacement strategies in associative mapping schemes play an important role in cache hit rate performance. This survey paper proposes a classification of these strategies with detailed discussion on their advantages and disadvantages.