Abstract:
External loopback testing is an industry standard test for serializer-deserializer (SERDES) interfaces, and it is used to test for at-speed defects in the analog transmis...Show MoreMetadata
Abstract:
External loopback testing is an industry standard test for serializer-deserializer (SERDES) interfaces, and it is used to test for at-speed defects in the analog transmission (TX) and reception (RX) buffers. The specific test involves sending pseudorandom bit sequence (PRBS) at high speed from the TX side, looping on the load-board and receiving on the RX side where the sequence is checked to calculate bit error rate (BER). To achieve parametric coverage on the buffers, it is required to have tester access at the SERDES pins. However, the on-board component populated for this tester access may lead to poor channel insertion and return loss due to reflections from these additional components. This, in turn, may lead to unacceptable BER at higher data rates. Consequently, it is a common practice to use one type of load-board for parametric/DC testing and another type for AC/at-speed testing. This paper describes a dedicated production load-board that is designed to achieve tester access on the SERDES pins using a resistor network. Using this load-board, external loopback could be operated successfully up to 20Gbps without sacrificing parametric test capability.
Published in: 2016 IEEE International Test Conference (ITC)
Date of Conference: 15-17 November 2016
Date Added to IEEE Xplore: 05 January 2017
ISBN Information:
Electronic ISSN: 2378-2250