ASIC design of a low-complexity K-best Viterbi decoder for IoT applications

To develop IoT sensor, research on low-cost and low-power wireless transceiver is necessary. Inside wireless transceiver, Viterbi decoder (VD) is one of the most complex but important block. VD is used in a receiver for decoding convolutional code from the transmitter and simultaneously correct bit errors. In addition, it is ceaselessly working circuit in a wireless transceiver, therefore it consumes a lot of power. This means that developing small and low power VD is one of the steps to make a wireless transceiver for IoT applications. In this paper, we propose K-best VD to simplify the circuit while keeping the same error correction performance. The K-best VD is narrowing down the number of paths of the trellis to K, on the basis of M-algorithm. We evaluate the performance of K-best VD by running the simulation and implement it with Verilog HDL. Our simulation result shows that the K-best VD achieves the same Packet Error Rate (PER) when K = 4 as the conventional. Finally, as an ASIC synthesis results, our hardware can reduce 91% of power consumption and 69% of the area.