RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer

Switch allocation is the critical pipeline stage for network-on-chips (NoCs) and it is influenced by the order of packets in input buffers. Traditional input-queued routers in NoCs only have a small number of virtual channels (VCs) and the packets in a VC are organized in fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the switch allocator. HoL blocking significantly degrades the efficiency of switch allocation as well as the performance of NoCs. In this paper, we propose to utilize reorder buffer (RoB) techniques to mitigate HoL blocking and accelerate switch allocation and thus reduce the latency of NoCs. We propose to design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packet. RoBs reduce the conflicts in switch allocation and can efficiently increase matching number in switch allocation. We design RoB-Router based on traditional input-queued routers in a lightweight fashion considering the trade-off between performance and cost. Our design can be extended to most state-of-the-art input-queued routers. Evaluation results show that RoB-Router can achieve 46% and 15.7% performance improvement in packet latency under synthetic traffic and traces from PARSEC than current most efficient switch allocator TS-Router, and the cost of energy and area is moderate.