A study on fast motion estimation algorithm

This paper presents a new fast motion estimation algorithm. It searches groups of 4-pixels simultaneously and uses the value concatenated the absolute difference of upper 2-bit with the exclusive OR of the lower 6-bit. The search accuracy results show that the sum of absolute difference value is increased 4 of 7 video sequences when compared to the full-search algorithm with 4-bit absolute difference accumulator. The circuit was described in Verilog HDL and synthesized to Altera EP4CE30F23I7 FPGA. The synthesis results show that the required cycle is reduced by 61%, the circuit size is reduced by 15.2% and the operating frequency is increased from 334.67 MHz to 616.90 MHz when compared to the full-search algorithm with 4-bit absolute difference accumulator.