The study of warpage of a flip chip embedded trace substrate

It is a trend of electronic packaging for light weight and thin package due to the increasing demand for 3C electronics and adaptive devices. As the device get smaller and lighter the substrate of the package get thinner and more complex. Therefore, it is an issue of substrate warpage due to factors such as shrinkage rate, uneven stress distribution in the substrate, and layout of copper layer, and these warpage can generate failure modes of the electric contacting between solder bump and solder pad[1–4]. Here, we present the investigation of the warpage of the embedded trace substrate of Flip-chip chip size package (FCCSP-ETS). Factors of layer thickness, difference of thermal expansion coefficient, and Young's module difference, and curing temperature are investigated based on Timoshenko beam theory. In addition, a 3D optical profiler and a shadow moire technique were used to verify the warpage of a sample FCCSP — ETS substrate under various process parameters.