Crosstalk and SSO noise minimize optimization of high speed and high-pin-count 3D PKG-VERTICAL CONNECTION UNIT

This paper discussed how to reduce cross talk and SSO noise to improve signal integrity for 3D PKG-VERTICAL CONNECTION UNIT. Due to the demand of high level IC integration, 3D packaging technology with multi-dies/chips in one package get rapid development. Traditional wire-bond multi-die stack package type have been unable to meet the challenge. TSV process seems to be an ideal solution, but with high cost and low yield. Another 3D packaging solution is VERTICAL CONNECTION UNIT, which leads each chip circuit traces to outlets and then interconnect outlets by traces on side wall. It makes large amounts of dies stack much easier. However, as die number increase and size scaling down, interconnect circuit will get more complex and signal integrity issue will be nerve-wracking. This paper chooses embedded storage product based on 32 die NAND Flash to study its SI performance, and make a benchmark with wire bonding package and TSV-based package. Furthermore, study optimization method based on original design, such as to change appropriate die pad order, to optimize ball assignment pattern, to change trace width/space, to add ground shielding and to minimize high speed signal trace length. Finally, crosstalk was significantly minimized and SSO noise was restrained effectively. SI performance can get ~11% improved. Performance comparison results show that VERTICAL CONNECTION UNIT PKG > TSV PKG > WB PKG. So it can be predicted that this 3D PKG will get more application in high capacity and high speed storage product.