Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling

A tunnel field‐effect transistor (TFET) in which the dominant carrier tunneling occurs in a direction that is in line with the gate electric field, shows great promise for sub‐0.6 V operation. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer‐drain overlap on the device characteristics of such silicon TFETs is reported in this chapter. It is demonstrated that a supersteep subthreshold swing and a significantly reduced OFF‐state current
I_OFF
can be achieved by appropriate designing of the spacer‐drain overlap. An investigation of the influence of the drain potential on the device characteristics reveals that the absence of a tunnel‐resistance limited region results in long‐channel metal oxide semiconductor FET‐like output characteristics for such a structure. Short‐channel effects, such as drain‐induced barrier lowering, are also greatly suppressed in it. Results of an investigation of the scaling properties of such devices are also reported.