CSP package development: the 4.0 manufactur1ng process for /spl mu/BGA(R)

A primary concern to anyone utilizing a new technology for high-density electronics is keeping development costs under control, optimization of existing manufacturing capability and minimizing the time-to-market. Chip-scale array package families for silicon products are already in the marketplace to assist the engineer and designer in meeting more demanding goals for electronic miniaturization. The significant advantage to employing the miniature chip-scale packaging technology is threefold; higher component density, more efficient assembly automation and enhanced product performance. Key factors that an engineer should consider before developing the product using CSP may include physical features and construction of the device, environmental or operating conditions for the end product, substrate material limitations and device attachment methodology. The course will present a detailed overview of industry trends in chip-scale package methodology and review the current status of standards for CSP. Material presented will assist the product developer in selecting and/or specifying specific physical attributes of the package structure. In addition, a step-by-step process description for the low cost /spl mu/BGA package assembly will be outlined. The package assembly process presented will feature the automated 4.0 in-line configured for the new RAMBUS high-speed memory (RDRAM) adapting the most widely used chip-scale or chip-size package technology, /spl mu/BGA.