Red Baron: Near/post-silicon SoC cache coherence stress tester

Cache coherent interconnects in modern SoC designs represent a complex design verification challenge. Coherence protocols trigger complex interactions between the heterogeneous mixes of caches and other system masters that comprise these SoCs. Furthermore, most coherence bugs are very sensitive to the exact timing and sequence of operations, and hence are difficult to target. Traditional DV only covers a limited portion of the state-space before the device tapeout. Red Baron is a SoC system level cache coherence stress tester which automatically generates testcases on the fly, taking into account the behavior of the CPU's cache, IO coherence, system memory and interconnect. This auto-generation methodology allows it to scale through the entire SoC design phases, from RTL simulation, emulation to silicon. This paper presents Red Baron's design, implementation and accomplishments on TI multicore SoCs.