A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

This paper presents the design of 10-bit, 40-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). A new asynchronous control structure is proposed. To reduce the power consumption, the monotonic capacitor switching procedure is used. To enhance the linearity of ADC, a two-phase non-overlapping clock is used. In order to improve the speed of comparison, redundant MOS transistor is added to the comparator. The prototype was implemented in 0.18pm 1P6M CMOS process. Under a 1.8-V supply and a 40-MS/s sampling rate, the power consumption of SAR ADC is only 0.775mW.