Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation

Ladder wave digital filters is a class of IIR digital filters derived from double resistively terminated ladder networks, which gives them good stability and low sensitivity to variations in the element values. An approach to design maximally fast bit-serial ladder wave digital filters is presented based on the numerically equivalent state-space representation of the signal-flow graph. An algorithm for finding the minimal sample period from the numerically equivalent state-space representation is also given. Maximally fast filters is an efficient way to achieve low power consumption on the algorithmic level. Further, we show an approach to map the operations to an optimal hardware structure, that can be implemented using bit-parallel, digit-serial, or bit-serial arithmetic.