The immunity of doping-less junctionless transistor variations including the line edge roughness

In this paper, a new method to restrain the impact of line edge roughness (LER) on Junctionless transistor is explored. The charge-plasma concept is employed for Junctionless transistor to form S/D N-region in doping-less silicon film by choosing an appropriate metal workfunction electrode. The electrical characteristics of doping-less Junctionless transistor are investigated using numerical simulation and compared with conventional Junctionless transistor. The results show that the doping-less Junctionless transistor has superior immunity to LER and has a better On/Off current ratio. It implies that the doping-less structure is an useful solution to suppress the variation brought by lithography and etching process efficiently.