Inductance to DC resistance ratio optimization of on-chip closed-core spiral power inductors

In this paper, on-chip closed-core spiral inductors are systematically designed and analyzed for inductance to dc resistance ratio optimization. Both theoretical calculations and numerical simulations are performed and the results agree well with each other. Results show that on-chip closed-core spiral power inductors should have only one turn. The impacts of the required inductance value, inductor area, core thickness, metal thickness, and core shape are also studied. These results also show that with improvements in material and fabrication capability, it is possible to boost the inductance to dc resistance ratio of current on-chip power inductors by over ten times.