Mechanical stress impact on CMOS low supply voltage bangap reference circuit

A model of a low supply voltage bandgap reference circuit has been developed to determine the circuit response to parameter drifts caused by the mechanical stress from packaging. Test chips have been implemented in 0.35 micron CMOS technology to determine statistically which features of the circuit are the main contributors to the observed stress sensitivity. After three-temperature measurements of devices on wafer and molded in SOIC-8 package, it has been confirmed the predicted reduction with (0.3 ÷ 0.4) percent of the drift of base-emitter voltage for PNP bipolar transistors. It has been proven that main contributors are mismatches between the MOSFETs and the resistors which is a good basis for future work in the same field.