Analysis of the impact of proximity correction algorithms on circuit performance

Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.