Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices

A Threshold Logic Gate (TLG) performs weighted summation of multiple binary inputs and compares the summation with a threshold. Different logic functions can be implemented by reconfiguring the weights and threshold of the same TLG circuit. This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current-mode weighted summation of binary inputs, whereas, the low voltage fast switching spintronic threshold device carries out the threshold operation in an energy efficient manner. The proposed STLG operates at a small terminal voltage of 50 mV, resulting in ultra-low energy consumption. A bottom-up cross-layer simulation framework is developed to synthesize and map large scale digital logic functions to the proposed STLG circuits. The simulation results of ISCAS-85 benchmarks show that the proposed STLG based reconfigurable logic hardware can achieve two orders lower Energy-Delay Product (EDP) compared with state-of-the-art CMOS Field Programmable Gate Arrays (FPGA), and smaller EDP compared to large scale Memristive Threshold Logic (MTL) based FPGA. Moreover, the ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared to MTL design.