Trellis based check node processing for nonbinary LDPC decoding using power representation

Check node processing dominates the complexity of nonbinary LDPC decoding. Trellis based min-max algorithm[1] can reduce the computation complexity and generate the message from check node to variable node in parallel. In this paper, power representation is used to implement check node processor, adder structures over GF(q) using power representation in trellis based check node processing are proposed. And power representation can make overall decoder architecture simpler.