A low power prototype for a 3D discrete wavelet transform processor

This paper presents a low power prototype of a 3-D discrete wavelet transform processor. It illustrates the design flow used in developing the prototype, and the mapping and verification starting from the high level modeling of the chip design and concluding with the low level implementation details at the transistor level. The main application of this architecture is toward 3-D MRI data, but other applications will benefit from the 3-D DWT as well, such as digital broadcast. The processor has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype processor is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power and utilization have been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipates 0.5 W of power. The prototype processor uses a 16-bit adder, 16-bit Booth multiplier and 1 KB cache with a maximum of 64-bit data bandwidth. Lower power has been achieved by using low power building blocks and the minimal number of computational units with high throughput.