A Hybrid Approach to FPGA Configuration Scrubbing

This paper describes a FPGA configuration scrubbing approach for Xilinx 7-Series FPGAs that combines the high-speed internal scrubbing available within these devices with an external scrubber. The internal scrubbing unit continuously monitors the frames of the FPGA configuration memory and corrects single-bit frame errors and is used to detect multi-bit frame errors. Multi-bit upsets are repaired by means of a secondary scrubbing mechanism that is primarily external to the FPGA fabric. This Xilinx 7-Series hybrid configuration scrubbing architecture scans 25,636,224 bits of the XC7Z020 device in several microseconds and detects upsets within 8 ms and then corrects most multi-cell upsets in under an additional 6 ms. This configuration scrubber was validated with configuration fault injection and neutron radiation testing.