Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality Systems

The ongoing trend to integrate multiple functions with different criticalities on a single platform calls for a robust on-chip communication infrastructure in which subsystems of different criticalities can coexist and interact. A fundamental prerequisite for such a platform is to eliminate any interference between safety-critical functions and non safety-critical ones. Furthermore, as mixed-criticality systems often comprise heterogeneous subsystems, the platform shall support different timing models (e.g., periodic and sporadic activities). This paper introduces an extension layer for the Network Interface (NI) of a network-on-a-chip in order to establish temporal and spatial partitioning over the entire chip. We describe how chip-wide segregation between different subsystems assures the absence of interference for time-triggered messages and bounded latencies for rate-constrained messages. The configuration of the NIs establishes guarding windows for time-triggered messages and traffic shaping of rate-constrained messages.