Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems

This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r=1/3 and the constraint length K= 9 (256 states). This chip is targeted for high speed convolutional decoding for next generation wireless applications. The Add-Compare-Select (ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the trace-back operation. The chip was implemented using 0.5 /spl mu/m CMOS technology and is operative at 20 Mbps under 3.3 V and at 2 Mbps under 1.8 V. The power dissipation is only 9.8 mW at 2 Mbps operation under 1.8 V.