Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction

For high-speed circuits, on-chip inductance can no longer be ignored. This paper deals with inductance in the presence of multilayered meshes used for on-chip power supplies. We have shown ways of designing power/ground (p/g) mesh that reduces inductance. Accurate 3-dimensional inductance extraction problem is intractable for large chips. We have demonstrated the feasibility of using flexible-accuracy empirical formulae for fast determination of inductance. We have reported results obtained from a real chip.