A field programmable system chip which combines FPGA and ASIC circuitry

The industry's first combination of FPGA and ASIC technologies is discussed in this paper. This chip known as Field Programmable System Chip (FPSC), combines a regular array of SRAM based FPGA programmable function units (PFUs) and an ASIC area in which any ASIC application which fits the usable area can be implemented. An interface block allows the transfer of data and clocks between the two circuit types. An additional feature is the ability to "program" the ASIC area using RAM bits in the FPGA bit stream that are set aside for this purpose providing the user added flexibility. This paper will describe the OR3TP12, an FPGA device with embedded 66 MHz/64 bits PCI core. A circuit allowing the user to program the FPGA through the PCI interface is also discussed.