New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS ICs. The layout rules are extracted from the experimental test chips with latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental test chips. Through detailed experimental verification, including the temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-/spl mu/m bulk CMOS technology.