A single-phase dynamic phasor estimation system: Analysis of performance and computational cost

This paper presents a new single-phase technique for dynamic phasor estimation using a sample by sample digital processing approach. The estimation process is performed in three stages. In the first stage, an efficient FIR filtering of the input signal is made to reject out-of-band and harmonic interference. The second stage uses a parameterized EPLL to track amplitude, phase, frequency and ROCOF. The final stage compensates the delay and any possible phase and amplitude distortion. The proposed design is compared against a well known window DFT method known as IpD
²
FT, which requires a large buffer and iterative process for each report. The goal is to develop a PMU system compliant with the IEEE Std. C37.118.1a and compare both algorithms in terms of performance and computational cost.