On-the-fly programmable hardware for networks

Ongoing research in adaptive protocols and active networks has presumed that flexibility is offered exclusively through software systems, and the performance implications have generated considerable skepticism. The programmable protocol processing pipeline (P4) exploits the dynamic reconfigurability of RAM based field programmable gate arrays (FPGAs) to provide both hardware performance and dynamic functionality to network components. We use forward error correction (FEC) as an example of a protocol processing function which we insert and remove from the protocol stack on an as-needed basis. Our measurements show that the P4 is able to process the data stream at OC-3 (155 Mbps) link rate, and consequently improve the TCP performance in noisy environments.