A DSP-based implementation of a turbo-decoder

This paper focuses on a DSP based implementation of a decoder for a simple turbo-code, consisting of two constituent codes of constraint length three and a 192 bit block interleaver. With three full iterations of the SOVA-based turbo-decoder executing on a single DSP chip, a data rate of approximately 10 kbps can be achieved. This implementation is then compared against a Viterbi decoder for the "NASA standard" constraint length seven convolutional code.