Power integrity modeling and measurement of TSV-based 3D IC system with application to the analysis of seven-chip stack

This paper presents power integrity modeling and measurement of through-silicon via (TSV)-based 3D IC system. To leverage the accuracy of a full-wave approach and shorter computational time of a circuit approach, a hybrid full-wave and circuit approach is proposed to model each individual chip consisting of TSVs, on-chip power grids and decoupling capacitors. A cascaded scattering matrix approach is used to model the 3D IC system by combining the results for individual chips, packages and boards. The hybrid modeling approach is demonstrated on a 7-chip stack consisting of 6 via-last and 1 via-middle chips. Modeling results show good correlation with measurement from 0.1 GHz to 20.1 GHz. Power integrity analysis is performed to show the effects of TSVs and vertical natural capacitors (VNCAPs) on the power distribution network in individual chips and the 7-chip stack. The passive VNCAPs in the 7-chip stack are also compared with active capacitors based on measurement. Finally, both modeling and measurement results for a prototype consisting of the 7 stacked chips mounted on a BGA substrate and a PCB are presented. This is probably the first comprehensive power integrity modeling, measurement and analysis of such a complete TSV-based 3D IC system at both chip and board levels.