Symbol timing recovery using digital spectral line method for 16-CAP VDSL system

This paper presents a new digital spectral line symbol timing recovery method for 16-CAP VDSL system. The proposed method resolves the digital implementation issues of the analog counterpart in two ways: (i) it avoids the costly linear phase bandpass filter that would otherwise be necessary, and (ii) it resolves the bandwidth expansion problem by using a single-sided pre-filter pair. With the architectural simplicity, its lower-frequency sampling clock offers an inexpensive implementation for the high speed timing recovery. Simulation shows that the jitter performance of the proposed method approaches to the theoretical limit especially for the transmission distance of less than 200 meters.