A clock tree based gated driver in low power delay buffer

A low power is emerged as a principle theme in today's electronics industry. The delay buffer uses several new techniques to reduce the power consumption. The ring counter with clock gated C-element method can effectively eliminates excessive data transition than conventional R-S flip flop clock gated method. In the ring counter double edge trigger flip flops are used to reduce the operating frequency by half. This paper focuses on the power dissipation during the Write operation in CMOS SRAM cell. In the Proposed SRAM cell, includes two more trail Transistors in the pull down path for proper charging and discharging of Bit Lines. The power dissipated in Proposed SRAM cell reduced by 12-38% in comparison to Conventional SRAM cell. And a octree based gated driver tree technique is also Proposed instead of quad tree for the clock distribution network can eliminate the power wasted on drivers that need not be activated.