A capacitor-less low drop-out voltage regulator for SoC applications

A capacitor-less low drop-out (LDO) regulator for SoC applications with buffer based compensation technique is proposed in this paper. The 1.6 V LDO with a power supply of 1.8 V is implemented in GPDK 0.18 μm CMOS technology and it achieves a PSRR of 70 dB up to 1 kHz for load currents up to 10 mA. It makes use of PMOS folded cascode error amplifier to lower the flicker noise. Simulation results verify that the proposed LDO is stable for a capacitive load from 0 to 30 pF and with a load capability of 10 mA and has a drop-out voltage of 200 mV. The layout of the design shows that the area acquired on the chip is approximately equal to 0.79 mm².