Performance analysis for full adder with Zipper logic

With the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other logic the problem may arise with stored values. During pre-charge, the stored output can affect the circuit. In this paper, we propose Zipper logic for adder circuit so that it prevents any leakage due to stored charge. It also avoids the need of an additional inverter. The proposed adder is designed using cadence virtuoso at 45nm with the supply voltage of 1.2V. This improves the speed of operation by replacing inverter with N P block in alternate fashion.