Crosstalk mitigation of network on chip: An analytical review

As per International Technology Roadmap of Semiconductors (ITRS) Network on chip (NoC) becomes suitable example of the integration of several cores on single die. Now a day's die size is continuously growing larger but, at the same time, minimum feature size is continuously shrinking. Although smaller transistor size can result in smaller circuit delay, a smaller feature size for interconnects does not reduce the signal propagation delay; thus, the signal propagation delay in interconnects has been the dominant factor in determining the delay of a circuit. To lighten this problem, interconnects are made thicker to reduce the sheet resistance. Unfortunately, this induces crosstalk noises between adjacent interconnects because of capacitive and inductive coupling. This is referred to as a signal integrity problem, and it is extremely difficult to detect. This paper provides the comparative analysis of various error correction code like-BSC, DAP, MDR, SEC, CADEC and JTEC. A comparative analysis has been based on the block-size, power dissipation, area, overhead, and path delay, algorithm structure, processing time, speed and reliability. These analyses conclude best error correction technique.