Optimization of reconfigurable fabric of DSP processor with image processing

In recent scenario, design complexity increases which motivate system designer to innovate continuously. While designing complex system with tight coupling, various block designing is become a choice. The strongly emerging class Coarse-Grained Reconfigurable Architecture (CGRA), is currently receiving due attention having excellent performance as well as flexibility in fabrication. CGRA is having one of the important blocks as reconfigurable array or fabric. In this paper, design of reconfigurable fabric with various combinations of processing element is presented. Also this design is analyze with area, power and delay t achieve optimization of DSP processor using various FPGA.