Design of high performance parallel self timed adder

The Parallel Self Timed adder (PASTA) is based on a recursive formulation for performing multi bit binary addition. The operation is parallel for those bits and do not need any of the carry chain propagation. The main objective of this paper is to reduce the power consumption and also to increase the performance. The existing design attains good performance over random operand conditions without any speedup circuit. The time spent for the input binary data can process quickly so that the delay can be reduced. The Parallel Self Timed Adder uses half adder along with multiplexer to minimize the number of interconnects. Average power consumption is found to be 0.09mW and the delay is found to be 0.021ns using 45nm technology. Proposed design achieves less power consumption when compared with CLA.