Design of high speed conditional push pull pulsed latch

In this paper, conditional push pull pulsed latch (CPPPL) is designed using Tanner tool. This latch is compared with other existing flip-flops. Total 12 flip-flops are compared with CPPPL which belong to different logic styles. Comparison is done through various parameters like energy, delay. From comparative analysis, it is found that CPPPL is efficient for balanced ED applications.