A high-gain, third-order analogue signal processing ASIC for DC-coupled CdZnTe detectors

In order to read out the signal of CdZnTe detectors, this paper presents a high-gain, third-order analogue signal processing application specific integrated circuit (ASIC). The charge generated in detectors can be amplified and shaped by this circuit. Dual-stage charge sensitive amplifier and baseline holder are utilized to compensate the leakage current from DC-coupled detectors. A novel shaper is proposed to improve the output amplitude and achieve high gain. A high-order shaper in our previous work is also presented for comparison. The proposed ASIC has been designed and verified in a standard commercial 2P4M 0.35μm CMOS process. The die area of one channel is 975 μm × 142 μm. The gain is 185 mV/fC at the peaking time of 1 μs. The peaking time can be adjusted from 1 μs to 3 μs. The maximum leakage current of 5 nA can be compensated.