A VLSI architecture for real-time gradient guided image filtering

High performance filtering has been in ever increasing demand for a range of applications, especially for real-time image/video processing. Guided image filter is one of the widely used image filters. Among them, the gradient domain guided image filter for edge-preserving smoothing and for mitigating the halo-artifacts problem existed in the current guided image filters is reported recently. Due to its computation complexity and the requirement of global pixel values in the computation, there is no existing VLSI implementation of gradient domain guided image filter. This paper presents such a VLSI architecture incorporated with techniques to reduce computation complexity and increase processing throughput. Subsampling technique is adopted in the design to save computation cost in terms of size and power consumption, without visually hampering the filtering result. Parallel structure is used at the output stage to restore the full image size and to achieve high throughput. Based on the STM 90-nm CMOS technology, the synthesis result shows that the proposed architecture is able to support Full-HD (1920 × 1080) image filtering at a throughput above 60 frame/s, with a design area of 726671.6μm
²
and power consumption of 9.85mW. Compared to the existing design, it can achieve two times higher throughput, and has 11.25% smaller size and 56.3% lower power consumption.