A novel simulation based approach for trace signal selection in silicon debug

With the fabrication technology fast approaching 7nm, post-silicon validation has become an integral part of integrated circuit design to capture and eliminate functional bugs that escape pre-silicon validation. The major roadblock in post-silicon functional verification is limited observability of internal signals in a design. A possible solution to address this roadblock is to make use of embedded memories on chip called trace buffers. The amount of debug data that can be acquired from the trace buffer depends on its width and depth. The width of the trace buffer limits the number of signals that can be traced and the depth of the trace buffer limits the number of samples that can be acquired. Using the acquired data from the trace buffer, the values of other nodes in the circuit can be reconstructed. These trace buffers have limited area, hence only a few critical signals can be recorded by it. In this work we used the simulated annealing heuristic to select trace signals. We developed this idea from the fact that trace signal selection can be viewed as a bi-partitioning problem, the set of flip-flops being tapped onto the trace buffer is one partition and remaining flip-flops form the other partition. Experimental results demonstrate that our approach can result in better restoration ratio compared to the state-of-the-art techniques.